Re: [Iverilog-devel] suspicious for-loop in eval_tree.cc (clang analysis)

[David F. <fa...@go...>]

Excellent, thanks!

On Fri, Jan 26, 2018 at 11:02 AM, Martin Whitaker <
ic...@ma...> wrote:

> David Fang via Iverilog-devel wrote:
>
>> Hi all,
>>
>> Clang analysis tools have identified the following snippet of code as
>> error-prone, in eval_tree.cc near line 712:
>>
>> for (unsigned idx = cnt ; idx < rv.len() ; idx += 1) {
>>    if (rv.get(idx) != pad)
>>      res = verinum::V0;
>>      break;
>>    }
>>
>> The break statement is unconditional, due to missing if open-brace, and
>> thus the for-loop executes at most once.  Is this a bug?
>>
>
> It is a bug. It's already been fixed in git, in both the master and the
> v10 branch.
>
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