Re: [Iverilog-devel] System verilog support in Icarus

[Martin W. <ic...@ma...>]

Niels Möller wrote:
> Martin Whitaker <ic...@ma...> writes:
>
>> Did you not see Cary's announcement about this (3 days ago)?
>>
>> If not, see the mailing list archive:
>>
>> https://sourceforge.net/p/iverilog/mailman/iverilog-devel/?viewmonth=201711
>
> Thanks for the pointer. And no, I didn't see it. It seems I was somehow
> kicked out from the list a few months ago and I haven't received list
> mail since April 23 (and I've not had any reason to post, either). First
> attempt at sending this question, a few days ago, failed with a
> non-member bounce, and I had to resubscribe.

I had similar problems. And the lack of response to my recent posts makes 
me wonder how many others we've lost...

> I'm reading Cary's announcement as good progress, but not yet quite
> useful for my purposes. And I totally agree it makes sense to have
> correctness for valid code as the top priority, even if my main interest
> is in stricter compile-time checks for incorrect code.

The checks are likely to be more tricky. At the moment the compiler 
calculates sensitivities down to the individual variable level, but to 
correctly implement the checks you need to know the sensitivities down to 
the individual bit level. The synthesis code in the compiler has the same 
problem when it is trying to detect latches.

Martin