[Iverilog-devel] Regarding root file

[chandan k. <ck9...@gm...>]

I am simulating full adder using a half adder. Files are as half_adder.v
and full_adder.v . I compile these files using half_adder.v as root file
using command
 $ iverilog -s half_adder.v -o sim_full_adder full_adder.v full_adder_tb.v

This gives an error
   error: unable to find the root module "half_adder" in verilog source.
        : Perhaps ''-s half_adder'' is incorrect?