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[Iverilog-devel] Fwd: commit 54feb8 *may* be a regression
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From: Jim P. <js...@ji...> - 2017-04-21 12:57:30
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Sorry if the below is a duplicate. I was having trouble posting to the
list and I can't tell from the archives whether or not this post got
through:
---------- Forwarded message ----------
From: Jim Peterson <js...@ji...>
To: ive...@li...
Cc:
Bcc:
Date: Thu, 20 Apr 2017 14:51:20 -0400
Subject: commit 54feb8 *may* be a regression
Devs,
Commit 54feb8... has altered the expected behavior of my simulations. In
particular, outputs at the beginning are now unknown (x) rather than the
expected value. Test code is at the end of this email (most of it is
copyright Xilinx). The results from compiling successive commits to git
are as follows:
0[sparkle:~/personal/src/github/iverilog]676: *git checkout
635adfc01eb3844deeefcf86d1a9a9b7c284369f*
Previous HEAD position was 28b446ca... Use correct type when printing
supply pull message
HEAD is now at 635adfc0... Fully support variable initialization in
tasks/functions/named blocks.
0[sparkle:~/personal/src/github/iverilog]677: *(make distclean;
./configure; make -j 4) >& /dev/null*
0[sparkle:~/personal/src/github/iverilog]678: *(sudo make install) >&
/dev/null*
[sudo] password for jspeter:
0[sparkle:~/personal/src/github/iverilog]679: *driver/iverilog -g2005-sv -o
tb.vvp -s tb ~/tb.v -Ttyp && ./tb.vvp *
VCD info: dumpfile test.vcd opened for output.
num: 000000, out: 0
num: x00000, out: 0
num: xx0000, out: 0
num: xxx000, out: 0
num: xxxx00, out: 0
num: xxxxx0, out: 0
num: xxxxxx, out: x
0[sparkle:~/personal/src/github/iverilog]680: *git checkout
54feb89bf540fb75abc31ede03cc9be444015e94*
Previous HEAD position was 635adfc0... Fully support variable
initialization in tasks/functions/named blocks.
HEAD is now at 54feb89b... For SystemVerilog, run variable initialization
before main simulation starts.
0[sparkle:~/personal/src/github/iverilog]681: *(make distclean;
./configure; make -j 4) >& /dev/null*
0[sparkle:~/personal/src/github/iverilog]682: *(sudo make install) >&
/dev/null*
[sudo] password for jspeter:
0[sparkle:~/personal/src/github/iverilog]683: *driver/iverilog -g2005-sv -o
tb.vvp -s tb ~/tb.v -Ttyp && ./tb.vvp *
VCD info: dumpfile test.vcd opened for output.
num: 000000, out: x * ****** first output is now x! *******
num: x00000, out: 0
num: xx0000, out: 0
num: xxx000, out: 0
num: xxxx00, out: 0
num: xxxxx0, out: 0
num: xxxxxx, out: x
0[sparkle:~/personal/src/github/iverilog]684:
I'm not sure if this is how SystemVerilog is supposed to work (i.e.,
whether this is a regression or an improvement... or, more particularly,
whether or not the 'always' statement in the LUT6 module should run once at
startup even if its inputs were initialized before simulation), but it
certainly throws a wrench in to some of my simulation tests. If this is
how it is supposed to work, I'm happy to fix my tests, but I thought you
ought to know.
--Jim
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT6.v,v
1.6 2007/06/01 00:22:57 yanx Exp $
////////////////////////////////////////////////////////////
///////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////
///////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library
Component
// / / 6-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT6.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace premitive with function; Remove buf.
// 05/30/07 - Change timescale to 1 ps / 1ps.
// End Revision
`timescale 1 ps / 1 ps
module LUT6 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
else
O = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}),
lut6_mux8 ( INIT[55:48], {I2, I1, I0}),
lut6_mux8 ( INIT[47:40], {I2, I1, I0}),
lut6_mux8 ( INIT[39:32], {I2, I1, I0}),
lut6_mux8 ( INIT[31:24], {I2, I1, I0}),
lut6_mux8 ( INIT[23:16], {I2, I1, I0}),
lut6_mux8 ( INIT[15:8], {I2, I1, I0}),
lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4,
I3});
end
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) &&
(d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) &&
(d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) &&
(d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}])
&&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}])
&&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}])
&&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
endmodule
module tb;
reg [5:0] num = 0;
reg res;
integer i;
initial begin
$dumpfile("test.vcd");
$dumpvars(0,tb);
num = 6'b000000;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bx00000;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bxx0000;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bxxx000;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bxxxx00;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bxxxxx0;
# 1;
$display("num: %b, out: %h",num,res);
num = 6'bxxxxxx;
# 1;
$display("num: %b, out: %h",num,res);
# 2 $finish;
end
LUT6 dut(
.O(res),
.I0(num[0]),
.I1(num[1]),
.I2(num[2]),
.I3(num[3]),
.I4(num[4]),
.I5(num[5])
);
defparam dut.INIT = 64'h8000000000000000;
endmodule
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