Re: [Iverilog-devel] Status of the verilog output target?

[Cary R. <cy...@ya...>]

The vlog95 target is currently the only mostly functional Verilog target and as the author of it I had intended to support the generate constructs. The problem is life, a new job etc. got in the way and I never have gotten around to finishing it. What you likely want is a Verilog target that can support different versions. I used 95 with the option to support signed because that was the base that many other tools would support. I also had a bit of a business need for it when I first started working on it. Making a target that supports different Verilog version is currently left as an exercise for the user. Much of the hard work has been done in the vlog95 target, though there are still a few places where the Icarus compiler mangles the original information too much to adequately decipher what was originally provided.
The VHDL target has not been touched or enhanced in a long time.

Cary 

    On Wednesday, February 22, 2017 1:41 PM, Niels Möller <ni...@ly...> wrote:
 

 Hi,

following advice on this list, I'm using yosys when I want to experiment
with synthesis. However, some of the modules in my design use system
verilog features, in particular, typedef struct packed { ... }, which
aren't supported by yosys.

I thought that was no problem, because I've read somewhere that icarus
verilog does have a verilog target which can be used as a system verilog
to verilog translator. But I'm having some trouble using it. The
"verilog" target seems to be disabled unless I edit the Makefile (it's
listed in NOTUSED rather than SUBDIRS), and I imagine there's some good
reason for that.

I then tried the vlog95 target, which is built by default. But that
doesn't support generate, which is a show stopper for me.

Finally I tried the vhdl output target (I think yosys supports vhdl
input, but I haven't tried it), but it seems to either be very slow or
not terminating. When I attach gdb after a few minutes, it's in the function
draw_all_signals and apparently never returning,

  1017          while (ivl_scope_type(parent) == IVL_SCT_GENERATE)
  Value returned is $1 = (ivl_scope_s *) 0x7f7299ee1df0
  (gdb) fin
  Run till exit from #0  draw_all_signals (scope=0x7f7299eddb00) at scope.cc:1017

and there it hangs.

I've just updated my iverilog checkout and recompiled, and it seems to
behave the same way with the latest version.

So is it possible to use Icarus Verilog as a translator from its
supported System Verilog subset to plain Verilog? Or is there some other
free software tool that can do that?

If not, I'll just have to reorganize my code a bit to avoid any System
Verilog features which aren't supported by *both* Icarus and yosys.

Best regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677.
Internet email is subject to wholesale government surveillance.

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