[Iverilog-devel] Status of the verilog output target?

[<ni...@ly...>]

Hi,

following advice on this list, I'm using yosys when I want to experiment
with synthesis. However, some of the modules in my design use system
verilog features, in particular, typedef struct packed { ... }, which
aren't supported by yosys.

I thought that was no problem, because I've read somewhere that icarus
verilog does have a verilog target which can be used as a system verilog
to verilog translator. But I'm having some trouble using it. The
"verilog" target seems to be disabled unless I edit the Makefile (it's
listed in NOTUSED rather than SUBDIRS), and I imagine there's some good
reason for that.

I then tried the vlog95 target, which is built by default. But that
doesn't support generate, which is a show stopper for me.

Finally I tried the vhdl output target (I think yosys supports vhdl
input, but I haven't tried it), but it seems to either be very slow or
not terminating. When I attach gdb after a few minutes, it's in the function
draw_all_signals and apparently never returning,

  1017          while (ivl_scope_type(parent) == IVL_SCT_GENERATE)
  Value returned is $1 = (ivl_scope_s *) 0x7f7299ee1df0
  (gdb) fin
  Run till exit from #0  draw_all_signals (scope=0x7f7299eddb00) at scope.cc:1017

and there it hangs.

I've just updated my iverilog checkout and recompiled, and it seems to
behave the same way with the latest version.

So is it possible to use Icarus Verilog as a translator from its
supported System Verilog subset to plain Verilog? Or is there some other
free software tool that can do that?

If not, I'll just have to reorganize my code a bit to avoid any System
Verilog features which aren't supported by *both* Icarus and yosys.

Best regards,
/Niels

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