[Iverilog-devel] wrong results in simple math equation

[thec <th...@ya...>]

`timescale 1ns/1ns

// in case you did receive two copies with the same content,
// just delete one.
// 6/66

module test;

        // Outputs
        wire w0,w1;

        initial
        begin
                $dumpfile("andx_gate.vcd");
                $dumpvars(0,test);
        end

        initial
        begin
                #100 $finish(2);
        end

	//
	//6/66 w0 and w1 should have the same results
	//
        assign #1 w0 = 1'b 0 * (1'b 1 - 1'b x);
        andx    andx0(.x0(1'b 0),.x1(1'b x),.y0(w1));

endmodule


module andx(x0,x1,y0);

input x0,x1;
output y0;

        assign #1 y0 = x0 * (1'b 1 - x1);

endmodule

// have fun
// 6/66