Re: [Iverilog-devel] Confusion about latches

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> As Yuri has suggested, take a look at Yosys - it's a much better tool
> for what you are trying to do.

I've now installed yosys, and done some initial tests with the example
synthesis script in the README.

Do you know if there's an easy way to get a summary of gate count from
yosys, similar to iverilog -t sizer? Or would I have to write out the
net list (in one of the several supported formats) and postprocess that?

Hmm, maybe it could work to let yosys do the synthesis, write out the
resulting net list in verilog format, and then feed that to iverilog -t
sizer?

Ideally, I'd like to get a break down by module, like iverilog -t sizer
does (even if I understand there are no sharp boundaries between modules
after synthesis). And it would also be nice to get the maximum gate
delay between flip flops.

Best regards,
/Niels

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