Re: [Iverilog-devel] Confusion about latches

[Guy H. <ghu...@gm...>]

Also note that iverilog comes up with the correct answer if all the
assignments are in the same always block:

module test

  (input [3:0] in,

   output reg [1:0] out);


  always @*

    begin

      out = { in[0]^in[2], in[1]^in[3] };

    end


endmodule

**** module/scope: test

     Flip-Flops   : 0

     Logic Gates  : 2

**** TOTALS

     Flip-Flops   : 0

     Logic Gates  : 2



On Wed, Nov 9, 2016 at 12:53 AM, Martin Whitaker <
mai...@ma...> wrote:

> Yuri Gribov wrote:
> > On Wed, Nov 9, 2016 at 8:35 AM, Niels Möller <ni...@ly...>
> wrote:
> >> Yuri Gribov <tet...@gm...> writes:
> >>
> >>> Also keep in mind that BLIF backend has been long abandoned so if you
> >>> are really interested in synthesis you may want to try other OSS
> >>> toolchains (namely Yosys).
> >>
> >> I don't plan to do real synthesis with iverilog, but I'd like to use the
> >> sizer target to get approximate gate count for my circuits and
> >> their parts.
> >
> > Be sure to run BLIF through ABC as Icarus generates suboptimal netlists.
>
> I was just about to say the same thing. iverilog does *no* optimisation of
> synthesised netlists, so
> the sizer output will grossly exaggerate the gate count.
>
> As Yuri has suggested, take a look at Yosys - it's a much better tool for
> what you are trying to do.
>
> Martin
>
>
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