Re: [Iverilog-devel] Confusion about latches

[Yuri G. <tet...@gm...>]

On Wed, Nov 9, 2016 at 8:35 AM, Niels Möller <ni...@ly...> wrote:
> Yuri Gribov <tet...@gm...> writes:
>
>> Also keep in mind that BLIF backend has been long abandoned so if you
>> are really interested in synthesis you may want to try other OSS
>> toolchains (namely Yosys).
>
> I don't plan to do real synthesis with iverilog, but I'd like to use the
> sizer target to get approximate gate count for my circuits and
> their parts.

Be sure to run BLIF through ABC as Icarus generates suboptimal netlists.

> I'm aware of Yosys, but I haven't tried it yet.
>
> Regards,
> /Niels
>
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