Re: [Iverilog-devel] Synthesis of memory assignment

[Martin W. <mai...@ma...>]

Niels Möller wrote:
> Hi,
>
> I tried to use the nice -t sizer target on my cpu
> (https://git.lysator.liu.se/nisse/instr16), but it failed on the
> register file (attached). There are a couple of errors
>
>    $ iverilog -t sizer reg-file.vl -o reg-file.txt
>    ...
>    reg-file.vl:57: sorry: Assignment to variable location in memory is not currently supported in synthesis.
>    reg-file.vl:62: sorry: Assignment to variable location in memory is not currently supported in synthesis.
>
> The expression is
>
> 	   rf[write_idx] <= write_data;
>
> inside an always @(posedge clk) block. I imagine this is non-trivial to
> fix, but I'd be very happy to be wrong.

Handling this relatively simple case might not be too hard, but making the tool robust (handling all 
the possible ways a user might use array words on the LHS of an assignment) would be a lot of work. 
For example, someone might quite reasonably write multiple assignments targeting different words or 
ranges of words in an array.

> BTW, iverlog -Wall also complains
>
>    reg-file.vl:37: warning: @* is sensitive to all 15 words in array 'rf'.
>
> on the combinatorial output block. Any explanation (or pointer thereto)
> on how to get this right is also appreciated. As far as I understand,
> I'd need to explicitly list the relevant signals (all the module inputs
> except clk and reset, I think) in the sensitivity list, and then
> convince myself that I still get the desired behavior in all cases.

The first thing to say is that this warning doesn't mean there's necessarily anything wrong with 
your code. If the code in your always block has no side effects, all it means is that your 
simulation may run more slowly than it otherwise might. So if your simulations are running fast 
enough, you can just disable this particular warning by

   -Wall -Wno-sensitivity-entire-array

There are a couple of other ways you could eliminate this warning:

1) Move the register file read outside the always @* block, e.g.

   assign stored_a_data = rf[a_idx];

   always @* begin
     if (a_idx == 15)
       a_data = 64'b0;
     else if (write_enable && a_idx == write_idx)
       a_data = write_data;
     else
       a_data = stored_a_data;
   end

2) Create an explicit sensitivity list, e.g.

   always @(write_enable or write_idx or write_data or a_idx or rf[a_idx]) begin
     if (a_idx == 15)
       a_data = 64'b0;
     else if (write_enable && a_idx == write_idx)
       a_data = write_data;
     else
       a_data = rf[a_idx];
   end

(in both cases, having separate always blocks for your three read ports may be slightly more 
efficient from a simulation point of view).

I would always go for option 1, as it protects against accidentally missing a sensitivity.

Martin