[Iverilog-devel] Synthesis of memory assignment

[<ni...@ly...>]

Hi,

I tried to use the nice -t sizer target on my cpu
(https://git.lysator.liu.se/nisse/instr16), but it failed on the
register file (attached). There are a couple of errors

  $ iverilog -t sizer reg-file.vl -o reg-file.txt
  ...
  reg-file.vl:57: sorry: Assignment to variable location in memory is not currently supported in synthesis.
  reg-file.vl:62: sorry: Assignment to variable location in memory is not currently supported in synthesis.

The expression is

	   rf[write_idx] <= write_data;

inside an always @(posedge clk) block. I imagine this is non-trivial to
fix, but I'd be very happy to be wrong.

BTW, iverlog -Wall also complains

  reg-file.vl:37: warning: @* is sensitive to all 15 words in array 'rf'.

on the combinatorial output block. Any explanation (or pointer thereto)
on how to get this right is also appreciated. As far as I understand,
I'd need to explicitly list the relevant signals (all the module inputs
except clk and reset, I think) in the sensitivity list, and then
convince myself that I still get the desired behavior in all cases.

Regards,
/Niels