Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Maciej S. <mac...@ce...>]

Hi,

Just a gentle reminder, so the issue does not get completely lost. Any
comment is welcome. I may rebase the pull request if necessary.

Regards,
Orson

On 03/29/2016 06:46 PM, Maciej Sumiński wrote:
> Hi,
> 
> I have just created a pull request for the mentioned patches [1]. The
> branch is rebased on the current master.
> 
> I have also found a minor bug, that must have been hard to trigger and
> observe. During net resolution (compile_cleanup()@vvp/compile.cc), nets
> are assigned the last observed scope (aka current_scope), which is not
> always the real parent scope.
> 
> The bug can be triggered by running the attached example:
> ----------------
> vpi error: cannot place value change callback on automatically allocated
> variable 'clk'
> ----------------
> even though clk should belong to 'auto_scope' module, which is a static
> scope. Upon closer inspection it has 'strange_label' scope assigned, as
> it was the last .scope directive in the a.out file. It is enough to
> comment out the scope label to make it run properly.
> 
> I have fixed it by simply correcting the scope after a net is created. I
> am not sure if that is the most elegant way of solving the problem, but
> I hope it helps to demonstrate the issue. The patch is not included in
> the pull request.
> 
> Regards,
> Orson
> 
> 1. https://github.com/steveicarus/iverilog/pull/95
> 
> On 03/22/2016 09:22 PM, Stephen Williams wrote:
>>
>> Sounds good, send me a pull request when you feel ready.
>>
>> On 03/22/2016 12:58 PM, Maciej Sumi?ski wrote:
>>> Hi Martin,
>>
>>> I see your point, I had overlooked the always block. I agree it has
>>> to be changed, and patches in the automatic_rebased branch should
>>> fix the problem.
>>
>>> Regards, Orson
>>
>>> On 03/22/2016 08:30 PM, Martin Whitaker wrote:
>>>> Hi Orson,
>>>>
>>>> Maciej Sumi?ski wrote:
>>>>> I presume you talk about vhdl_string & vhdl_image_attr tests.
>>>>> The variables causing warnings are initialized inside a module
>>>>> scope. If I understand the standard correctly (6.21 @
>>>>> 1800-2012), it is not required to explicitly declare such
>>>>> variables as static, because it is illegal for them to be
>>>>> automatic (see an example on p.91 @ 1800-2012).
>>>>
>>>> Yes, those are the tests I was talking about. Taking
>>>> vhdl_image_attr as an example, the relevant part of the vhdlpp
>>>> output is:
>>>>
>>>> always begin : __scope_1 bit[32'd7:32'd0] var_char   = "o"; int
>>>> var_int   = 32'd10; real var_real   = 12.34; time var_time   =
>>>> 10ns; ...
>>>>
>>>> These variables are declared inside a begin/end block, so
>>>> SystemVerilog permits them to be declared as static or automatic,
>>>> hence the rule about having an explicit static keyword applies.
>>>> The equivalent example on page 91 of 1800-2012 is
>>>>
>>>> initial begin int svar2 = 2; // static/automatic needed to show
>>>> intent ...
>>>>
>>>> To be sure I'm reading the standard correctly, I tried this
>>>> example
>>>>
>>>> module test();
>>>>
>>>> integer legal = 1;
>>>>
>>>> initial begin: named_block integer illegal = 1; end
>>>>
>>>> endmodule
>>>>
>>>> on another simulator. It accepted the declaration of 'legal' and
>>>> warned that the declaration of 'illegal' required an explicit
>>>> 'static' keyword.
>>>>
>>>>> Anyway, if you would rather vhdlpp emit lifetime for each
>>>>> variable, I pushed a fix to automatic_rebased branch [1] on
>>>>> github. It also contains patches to make Larry's use_func test
>>>>> case work and passes all the tests, so feel free to merge it.
>>>>
>>>> I'll leave this for Steve.
>>>>
>>>> Regards,
>>>>
>>>> Martin