Re: [Iverilog-devel] Iverilog support for synthesis thargeting Virtex - 4 FPGA - Reg.

[Larry D. <ldo...@re...>]

Ravi -

On Wed, Apr 13, 2016 at 11:32:37AM +0530, Ravi Selvaraj wrote:
> Are there any such commands for BLIF file generation with Icarus.

It sounds like you might be happier with Yosys
http://www.clifford.at/yosys/about.html

  - Larry