Re: [Iverilog-devel] System verilog support in Icarus

[Iztok J. <izt...@gm...>]

A few comments regarding the provided source.
1. I usually use logic for all signals in RTL code, I use wire only for
tristate signals
2. for coding registers always_ff is great, but the 'out' signal should not
be a wire, it should be logic/reg (this two are the same in SystemVerilog)
3. the out++ syntax is not appropriate for RTL, since it is not clear if
the assignment is blocking or not. I usually use ++ in bench code, inside
initial statements or for loops

Icarus has only a partial SystemVerilog support, not even all RTL features
are supported. In case somebody would like to create a table of supported
features, I am wiling to help with code examples, unit tests, with the
focus on RTL features.

Regards,
Iztok Jeras

On Wed, Mar 23, 2016 at 8:37 PM, Corey Olson <cor...@gm...> wrote:

> Correct me if I'm wrong, but I believe the 'out ++' portion is not
> standard Verilog.  Therefore it sounds like some SystemVerilog constructs
> are supported by Icarus and some are not.  Is there a list anywhere of the
> things that are supported?
>
> -Corey
>
> On Wed, Mar 23, 2016 at 1:34 PM, Larry Doolittle <ldo...@re...
> > wrote:
>
>> Krishnaraj -
>>
>> On Wed, Mar 23, 2016 at 01:56:02PM +0530, Krishnaraj Bhat wrote:
>> > Tried to compile a simple up-counter system Verilog module.
>> > But compilation fails.
>> > Could you please let me
>> > know whether the latest version (10.1) supports system verilog?
>>
>> I'm not a SystemVerilog language laywer.  I suspect the literal answer
>> is "no", there are odd corners of the language that don't work in
>> iverilog.  Practically, it's supposed to be usable now.
>>
>> I don't know why you think you can use non-blocking assignment to
>> a wire, or what "always_ff" is supposed to mean.  But the following
>> module compiles just fine under Icarus.  There are no SystemVerilog
>> language features used here, just ordinary Verilog.
>>
>> module up_counter (
>>   output reg [7:0] out,
>>   input  wire      enable,
>>   input  wire      clk,
>>   input  wire      reset
>> );
>> always @(posedge clk)
>>   if (reset) begin
>>     out <= 8'b0;
>>   end else if (enable) begin
>>     out ++;
>>   end
>> endmodule
>>
>>    - Larry
>>
>>
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>
>
>
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