Re: [Iverilog-devel] System verilog support in Icarus

[Jonathan D. <jb_...@ya...>]

I'm not sure about what features are and are not supported, but I believe that the 1800-2012 standard is available for free through the ieee, thanks to an Accelera program. For those of you who are not aware what always_ff or always_comb etc are supposed to do.I would expect that the module level  features (ie RTL features like these ) would be farther along than the class and package related features. But I haven't installed icarus for a while, so can't really comment on the present state.Jonathan 

Sent from Yahoo Mail on Android 
 
  On Wed, Mar 23, 2016 at 12:37 PM, Corey Olson<cor...@gm...> wrote:   Correct me if I'm wrong, but I believe the 'out ++' portion is not standard Verilog.  Therefore it sounds like some SystemVerilog constructs are supported by Icarus and some are not.  Is there a list anywhere of the things that are supported?

-Corey
On Wed, Mar 23, 2016 at 1:34 PM, Larry Doolittle <ldo...@re...> wrote:

Krishnaraj -

On Wed, Mar 23, 2016 at 01:56:02PM +0530, Krishnaraj Bhat wrote:
> Tried to compile a simple up-counter system Verilog module.
> But compilation fails.
> Could you please let me
> know whether the latest version (10.1) supports system verilog?

I'm not a SystemVerilog language laywer.  I suspect the literal answer
is "no", there are odd corners of the language that don't work in
iverilog.  Practically, it's supposed to be usable now.

I don't know why you think you can use non-blocking assignment to
a wire, or what "always_ff" is supposed to mean.  But the following
module compiles just fine under Icarus.  There are no SystemVerilog
language features used here, just ordinary Verilog.

module up_counter (
  output reg [7:0] out,
  input  wire      enable,
  input  wire      clk,
  input  wire      reset
);
always @(posedge clk)
  if (reset) begin
    out <= 8'b0;
  end else if (enable) begin
    out ++;
  end
endmodule

   - Larry

------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel


------------------------------------------------------------------------------
Transform Data into Opportunity.
Accelerate data analysis in your applications with
Intel Data Analytics Acceleration Library.
Click to learn more.
http://pubads.g.doubleclick.net/gampad/clk?id=278785351&iu=/4140_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel