Re: [Iverilog-devel] System verilog support in Icarus

[Larry D. <ldo...@re...>]

Krishnaraj -

On Wed, Mar 23, 2016 at 01:56:02PM +0530, Krishnaraj Bhat wrote:
> Tried to compile a simple up-counter system Verilog module.
> But compilation fails.
> Could you please let me
> know whether the latest version (10.1) supports system verilog?

I'm not a SystemVerilog language laywer.  I suspect the literal answer
is "no", there are odd corners of the language that don't work in
iverilog.  Practically, it's supposed to be usable now.

I don't know why you think you can use non-blocking assignment to
a wire, or what "always_ff" is supposed to mean.  But the following
module compiles just fine under Icarus.  There are no SystemVerilog
language features used here, just ordinary Verilog.

module up_counter (
  output reg [7:0] out,
  input  wire      enable,
  input  wire      clk,
  input  wire      reset    
);
always @(posedge clk)
  if (reset) begin 
    out <= 8'b0;
  end else if (enable) begin
    out ++;
  end
endmodule

   - Larry