Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Martin W. <mai...@ma...>]

Hi Orson,

Maciej Sumiński wrote:
> I presume you talk about vhdl_string & vhdl_image_attr tests. The
> variables causing warnings are initialized inside a module scope. If I
> understand the standard correctly (6.21 @ 1800-2012), it is not required
> to explicitly declare such variables as static, because it is illegal
> for them to be automatic (see an example on p.91 @ 1800-2012).

Yes, those are the tests I was talking about. Taking vhdl_image_attr as an example, the relevant 
part of the vhdlpp output is:

   always begin : __scope_1
     bit[32'd7:32'd0] var_char   = "o";
     int var_int   = 32'd10;
     real var_real   = 12.34;
     time var_time   = 10ns;
     ...

These variables are declared inside a begin/end block, so SystemVerilog permits them to be declared 
as static or automatic, hence the rule about having an explicit static keyword applies. The 
equivalent example on page 91 of 1800-2012 is

   initial begin
     int svar2 = 2; // static/automatic needed to show intent
     ...

To be sure I'm reading the standard correctly, I tried this example

   module test();

   integer legal = 1;

   initial begin: named_block
     integer illegal = 1;
   end

   endmodule

on another simulator. It accepted the declaration of 'legal' and warned that the declaration of 
'illegal' required an explicit 'static' keyword.

> Anyway, if you would rather vhdlpp emit lifetime for each variable, I
> pushed a fix to automatic_rebased branch [1] on github. It also contains
> patches to make Larry's use_func test case work and passes all the
> tests, so feel free to merge it.

I'll leave this for Steve.

Regards,

Martin