Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Maciej S. <mac...@ce...>]

On 03/19/2016 10:33 PM, Martin Whitaker wrote:
> Martin Whitaker wrote:
[snip]
> @Orson - two of the VHDL tests now fail. To fix them, vhdlpp needs to explicitly declare variables 
> inside blocks as static when the declaration includes an initialisation expression.

Hi Martin,

I presume you talk about vhdl_string & vhdl_image_attr tests. The
variables causing warnings are initialized inside a module scope. If I
understand the standard correctly (6.21 @ 1800-2012), it is not required
to explicitly declare such variables as static, because it is illegal
for them to be automatic (see an example on p.91 @ 1800-2012).

Anyway, if you would rather vhdlpp emit lifetime for each variable, I
pushed a fix to automatic_rebased branch [1] on github. It also contains
patches to make Larry's use_func test case work and passes all the
tests, so feel free to merge it.

Regards,
Orson

1. https://github.com/orsonmmz/iverilog/tree/automatic_rebased