[Iverilog-devel] VCD files comparator

[Maciej S. <mac...@ce...>]

Hi,

I had to compare HDL simulation results generated by a few simulators,
but unfortunately I could not find a piece of software that would handle
the files I got.

The main problem was the difference in handling buses: sometimes
reg[7:0] is saved as 8 single variables, sometimes as a 8-bit wide bus
(not to mention weirdness when handling multidimensional arrays).
Variable matching is usually done by lexical comparison, so it does not
work in such cases. As it has turned out, it was easier to write a new
comparator from scratch, rather than fix an existing one.

If you need something that resolves a similar problem, I encourage you
to take vcdiff [1] for a test drive. As it is still in testing phase,
please let me know if you find any issues.

Regards,
Orson

1. https://github.com/orsonmmz/vcdiff