Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Martin W. <mai...@ma...>]

Martin Whitaker wrote:
> I have a fix for variable initialisation in automatic functions (and tasks), which I will push once
> I've fixed some of the other issues.

I have pushed the fixes for these issues. Also included are:

   - if you select a SystemVerilog generation, variable initialisation
     specified as part of the declaration is now performed before any
     initial/always process is started (as required by the SystemVerilog
     standard)
   - default subroutine lifetimes are supported (in module/program/
     interface/package/class declarations)
   - tasks and functions can be explicitly declared as static
   - variables can be explicitly declared as static or automatic,
     although the compiler currently throws an error if the declaration
     is different to the default value
   - a warning is generated if static variables in tasks/functions/blocks
     are initialised in their declaration but not explicitly declared as
     static (IEEE1800 actually requires this to be an error, but I've
     made it a warning for now).

Do we want to backport these changes to v10? Currently v10 silently fails to run the variable 
initialisation in many cases.

@Orson - two of the VHDL tests now fail. To fix them, vhdlpp needs to explicitly declare variables 
inside blocks as static when the declaration includes an initialisation expression.