Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Martin W. <mai...@ma...>]

Maciej Sumiński wrote:
> Hi,
>
> Martin, thank you for the explanations. You are right, VHDL subprograms
> are automatic by default.
>
> Larry, there is a branch [1] that produces code in the way you have
> suggested. I believe the semantics is correct here.
>
> I had tried simply adding 'automatic' keyword to the function
> declaration, but it did not help. I am going to include the branch in
> the next pull request.

I have a fix for variable initialisation in automatic functions (and tasks), which I will push once 
I've fixed some of the other issues.

Martin