Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Martin W. <mai...@ma...>]

Larry Doolittle wrote:
> Friends -
>
> Just for fun, I added an additional test to this sample code.
>
> module test();
> function int rounded_down_power_of_two(input int value);
>   int n = 32'd0;
>   int temp;
>   //n = 32'd0;
>   temp = value;
>   while (temp > 32'd1) begin
>     temp = temp / 32'd2;
>     n = n + 32'd1;
>   end
>   return n;
> endfunction
> localparam value5 = rounded_down_power_of_two(34);
> localparam value3 = rounded_down_power_of_two(8);
> initial $display("%d %d", value5, value3);
> endmodule
>
> If n were considered static, I might expect this to print
>           5           8
> but in fact n seems to be initialized on every invocation
> (elaboration?) of rounded_down_power_of_two(), so it prints
>           5           3
> Martin, does this fit your understanding of how SystemVerilog
> is supposed to work?

Yes, because these are constant function calls, and there's a special rule for that:

"Constant function calls are evaluated at elaboration time. Their execution has no effect on the 
initial values of the variables used either at simulation time or among multiple invocations of a 
function at elaboration time. In each of these cases, the variables are initialized as they would be 
for normal simulation."

If you try

   $display("%d", rounded_down_power_of_two(34));
   $display("%d", rounded_down_power_of_two(8));

you will get

   5
   8

Having said that, I've just tried changing the initial value of n to 1, and it has no effect. The 
compiler doesn't seem to be generating the initialisation code. This is a bit of a surprise, as I 
was looking at the vlog95 target code generator at the weekend, and it has code to handle this case.

Martin