Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Martin W. <mai...@ma...>]

Larry Doolittle wrote:
> Martin -
>
> Thanks for looking into this.  I'm not much of a SystemVerilog
> standards guru.

Nor am I really - I mostly use traditional Verilog.

...
> Does the following version look better?  It does print "5".
> And Maciej, does it seem like it correctly captures the semantics
> of the original VHDL?
...
> function int rounded_down_power_of_two(input int value);
>   int n;
>   int temp;
>   n = 32'd0;
>   temp = value;
>   while (temp > 32'd1) begin
>     temp = temp / 32'd2;
>     n = n + 32'd1;
>   end
>   return n;
> endfunction
...

I think that's fine for this example. I'm not familiar with VHDL, but I'd guess it doesn't make 
variables static by default, so if a function contains any form of delay, vhdlpp should declare the 
emitted function to be automatic.

> It would be easier for vhdlpp to emit
>   int n; n = 32'd0;
>   int temp; temp = value;
> but that is not accepted by iverilog -g2005-sv.

Yes, SystemVerilog is like C - you can't mix declarations and statements.

Martin