Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Larry D. <ldo...@re...>]

Friends -

Just for fun, I added an additional test to this sample code.

module test();
function int rounded_down_power_of_two(input int value);
  int n = 32'd0;
  int temp;
  //n = 32'd0;
  temp = value;
  while (temp > 32'd1) begin
    temp = temp / 32'd2;
    n = n + 32'd1;
  end
  return n;
endfunction
localparam value5 = rounded_down_power_of_two(34);
localparam value3 = rounded_down_power_of_two(8);
initial $display("%d %d", value5, value3);
endmodule

If n were considered static, I might expect this to print
          5           8
but in fact n seems to be initialized on every invocation
(elaboration?) of rounded_down_power_of_two(), so it prints
          5           3
Martin, does this fit your understanding of how SystemVerilog
is supposed to work?

   - Larry