Re: [Iverilog-devel] SystemVerilog functions via vhdlpp

[Larry D. <ldo...@re...>]

Martin -

Thanks for looking into this.  I'm not much of a SystemVerilog
standards guru.

On Mon, Mar 14, 2016 at 08:16:41PM +0000, Martin Whitaker wrote:
> Extracting the rounded_down_power_of_two function from the output of vhdlpp and converting to a 
> simple SystemVerilog test case gives:
> 
>    module test();
> 
>    function int rounded_down_power_of_two(input int value);
>      int n = 32'd0;
>      int temp = value;
>      while (temp > 32'd1) begin
>        temp = temp / 32'd2;
>        n = n + 32'd1;
>      end
>      return n;
>    endfunction
> 
>    localparam value = rounded_down_power_of_two(34);
> 
>    initial begin
>      $display("%d", value);
>    end
> 
>    endmodule
> 
> This is illegal, because [...]

Does the following version look better?  It does print "5".
And Maciej, does it seem like it correctly captures the semantics
of the original VHDL?

module test();

function int rounded_down_power_of_two(input int value);
  int n; 
  int temp; 
  n = 32'd0;
  temp = value;
  while (temp > 32'd1) begin
    temp = temp / 32'd2;
    n = n + 32'd1;
  end
  return n;
endfunction

localparam value = rounded_down_power_of_two(34);

initial begin
  $display("%d", value);
end

endmodule

It would be easier for vhdlpp to emit
  int n; n = 32'd0;
  int temp; temp = value;
but that is not accepted by iverilog -g2005-sv.

   - Larry