[Iverilog-devel] SystemVerilog functions via vhdlpp

[Larry D. <ldo...@re...>]

Friends -

See attached test case for VHDL functions, which fails because the
width of bit_counter comes out as 1, not 4.  I'd like to thank
Maciej for huge strides towards making this work!  This has turned
into a SystemVerilog question.  With all the recent changes in
iverilog git master, I thought I should check if the problem is
still present.  It is.

It's a pretty small tar file, 3122 bytes spread across 7 files.
If you bypass the use of next_highest_power_of_two() in use_func.vhd, 
you get
$ make
iverilog -Wall -Wno-timescale -g2005-sv -civhdl.cfg  -o use_func_tb use_func_tb.v use_func.vhd
vvp -n use_func_tb  | awk -f testcode.awk
          3 PASS
But with the buggy next_highest_power_of_two() call in place,
out-of-the-tarball, you get
$ make
iverilog -Wall -Wno-timescale -g2005-sv -civhdl.cfg  -o use_func_tb use_func_tb.v use_func.vhd
vvp -n use_func_tb  | awk -f testcode.awk
         20 FAIL
make: *** [use_func_check] Error 1

Back on 28 Jan 2016, when I discussed this with Maciej,
he discovered that if you change the following line:
  int \temp =  \value ;
to
  int \temp ; \temp = \value ;
in the generated code, function next_highest_power_of_two(), then it
works correctly.  The question is if Icarus' SystemVerilog processing
should be fixed, or ivlpp should stop emitting broken SystemVerilog.

  - Larry