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From: Maciej S. <mac...@ce...> - 2016-03-08 08:52:49
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Yes, I had to change the tests. The reason is, now variables are emitted in corresponding process scopes, so there is no direct access to them from another module and these tests relied on that (i.e. I cannot check 'if(dut.variable == 42)' anymore). I will push the changes to the test repository soon. Regards, Orson On 03/07/2016 06:20 PM, Stephen Williams wrote: > > > This pull seems to have created a few new regressoins in > VHDL code. These fail now. Are there ivtest changes that > you need to push? > > > steve@icarus:~/icarus/eda/ivtest> diff regression_report-devel.txt > regression_report.txt > 2089c2089 > < vhdl_string_lim: Passed. > --- >> vhdl_string_lim: ==> Failed - running iverilog. > 2100c2100 > < vhdl_textio_read: Passed. > --- >> vhdl_textio_read: ==> Failed - running iverilog. > 2115c2115 > < vhdl_while: Passed. > --- >> vhdl_while: ==> Failed - running iverilog. > 2192c2192 > < Total=2187, Passed=2181, Failed=6, Not Implemented=0, Expected Fail=0 > --- >> Total=2187, Passed=2178, Failed=9, Not Implemented=0, Expected >> Fail=0 > > > On 03/07/2016 08:39 AM, Maciej Sumiński wrote: >> Hi, > >> There is a new branch [1] that contains a few fixes for vhdlpp and >> one for ivl. There are also tests to support the introduced changes >> [2]. > >> Again, it would be great if you could have a look at the ivl >> related commit [3]. When I executed a certain test [4], it seemed >> to me that slices were not correctly computed in a few cases. It >> should be fixed now. > >> The new pull request includes the previous one, so I have canceled >> the old request. > >> Regards, Orson > >> 1. https://github.com/steveicarus/iverilog/pull/92 2. >> https://github.com/orsonmmz/ivtest/tree/vhdlpp_fixes_test 3. >> https://github.com/orsonmmz/iverilog/commit/de775975e8d846c2a591a7889dd26c96b76acbc3 > > > 4. >> https://github.com/orsonmmz/ivtest/blob/b926f97f9b1ece5d8a09a9be6fd4b33407c67d59/ivltests/array_packed_2d.v > > > |