[Iverilog-devel] Pull request

[Maciej S. <mac...@ce...>]

Hi,

I have just created a new pull request [1] supported by unit tests [2].
Changes:

= vhdlpp
- support for basic loops (loop .. end loop)
- subtype declarations
- initial support for CHARACTER enums (LF & CR for now)
- system functions: now, shift_left, shift_right
- limited support for final wait statement
- concurrent assertion statements
- delayed assignment statements
- conditional assignments without the ending 'else' statement
- subprogram overloading (support for multiple functions with the same
name, but different parameters types)
- multidimensional arrays, only on the vhdlpp side (i.e. VHDL code is
translated but cannnot be executed yet)
- a bunch of fixes

= ivl
- part selection in multidimensional packed ports assignment

= vvp
- implemented vvp_net_fun_t::recv_vec4_pv()

It would be great if the ivl & vvp changes were reviewed more carefully.
recv_vec4_pv() seemed suspiciously simple, and I am afraid I might have
missed something important there.
Code responsible for part selection in multidimensional packed ports
assignment is based on the code I have seen in elab_expr.cc
(PEIdent::elaborate_expr_net_part_).

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/90
2. https://github.com/orsonmmz/ivtest/tree/subp_overload_test