Re: [Iverilog-devel] DDR3 simulations

[Martin W. <mai...@ma...>]

Hi Larry,

Larry Doolittle wrote:
> The original Micron readme.txt file covers ModelSim, NC-Verilog, and VCS.
> But most of my changes fix errors that would prevent correct execution
> on _any_ simulator.  What do other Icarus users do for DDR3 simulations?

I've used the Micron DDR2 and DDR3 models with Icarus (and NC-Verilog) over 
many years now. I've generally had to make one or two minor changes to 
suppress unwanted warnings (and to fix the odd bug). I've never bothered to 
run their testbench, so my comments apply to the basic DDR model only.

Looking at my testbench, I see I'm currently using ddr3.v v1.60, and have 
recorded the following changes:

// MTW, 06-Nov-09, modified check of reserved MR bits to eliminate warning 
when the
//                 address bus width is less than 14. Disabled power-up to RST_N
//                 and RST_N to CKE checks. Fixed bug in tCL check.
// MTW, 06-May-10, added option to suppress tWLS and tWLH timing checks. These
//                 produce lots of spurious warnings during levelling.

With these changes my tests run without any warnings.

I have also used ddr3.v v1.69, but as it uses a few SystemVerilog constructs, 
only with NC_Verilog. I haven't checked to see if the SV support in Icarus has 
improved enough to run this now.

The two big things you can do to speed up simulations, if your DRAM controller 
lets you, is to disable the power-up and reset delays, and to disable 
levelling. Even so, simulations run slowly in Icarus.

HTH,

Martin