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From: Larry D. <ldo...@re...> - 2016-01-19 16:57:46
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Friends - I have a habit of _not_ using external RAM on my FPGA designs. It usually seems better to me to schlep data directly to commodity computer hardware instead. But I have a project now that may force me to finally get my feet wet. I downloaded a DDR3 model from Micron, and hacked it enough to get partial success according to this script: set -e if ! test -e micron_ddr3.zip; then curl -o micron_ddr3.zip https://www.micron.com/~/media/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip; fi echo "e063c7c63e3453d04998a3a0af8f25c207bce0e72af33b572871d6df40d3d39d micron_ddr3.zip" | sha256sum -c DIR=`mktemp -d ddr_test_XXXXXX` cd $DIR unzip ../micron_ddr3.zip chmod a-x * chmod u+w * uudecode << EOT begin-base64 644 ddr3.patch.gz H4sIADjJnVYCA5VVbW/bNhD+HP2K+5BiFmQmpGwrsuR0TtphCNJkaWy0w4JM ky3a4aIXj6Kdot3++0hRkuWXpA0liMfjPUfe8eEpYrMZoCWga4gi3gkyzubH SjpaFYpSNhBCOwYHNiY9hPvyBdLzbMfrdY5w1QDhE4wNy7KajhTGQZgg4ioM 7nu2vYFxJWY4BEScTvsELN0NhwaoxtLFUsg+i4RvgNYdH8M0zqaP8DcTgnID KSWnYax6MX0MwtXcN6w92lPiYOxrL4IltJrKw2QRU7i7+eV2/O7y7NOviHj4 fsfwYddwn1n8jJkKsktw2wFLdc0gBZ1TDglNZtHdX+dn15ejagfysZo2zK8w TLAw1oMJnbMUPJixmAYsC7IFTfWMTsIc7s7PgvOL8QgQEGmI72ESpo/lnuy+ Sny309xT1Ux/PaZpJLeDquEs49Cq9wWngH3ZDUAH4BcqBhYQU4ewxrxou7G8 Tgm7l9MqqEDtOlBhtphZE6IkxQ2ncRZGkNOpYFlqRPuYfhU+UoXXFK1GW2yv 1Aek7/QRsVGHAHE8jOW7w92a7zWqwXibeAR7HbyX8biNJd/bBKusW2Ece3oP YmJYhlWKHohJeTXlrbQO2IpyFmdzQJ8lAtDcxriH8hWg9xFNbdx1ryZSzuek ByiDwyEc/qnc8WXacH+wWi0ApXA4UHPTmIapJ7U8ATSrrfYmMF9OBM3F0epB R70ebyVxPVGWDQcRWTZkNk484jxfNjZxdenoer2+1+vtTaTrKgIX3yZ/15Li RZBkES3HLdyGb6T70wQH8sE4IBv9f/AvJDx44oNBX4vTeDCwTV/R7Eq5uZU3 LpfFB56YeID3Hz5ITU5F83qk2WKDyq0k/NIaS9PL9viPjxfXF2PT9Nc34wXz POJhUiQWHzWgtaksjkFWlEndBqdAfHi+ySDEkqeQpQq69qO20CK4uFh7z75m YiFtnbdSve6kK0TzjF35h9j/e+i4bVdel6KrTvmJcboT3h1RtRPElwUvxqeg UjmlLG6Nf7+5PZYV32yDEgNZnatEvuwqh11Xo9rT6BWOojguHEmUPFxf8+VF zNd/prleXB7+u9GPQWS15CXkN/kbKon2g+tsEU6tab1izS24Xv+7uXniUCW5 JeRgAK4JP4MSveJrqe8b+3uu+vf67u66KmQEXVM7fPuWKKb/D6HaLiwRCQAA ==== EOT gunzip ddr3.patch.gz patch -p1 < ddr3.patch make A subsequent "make run" takes 3 minutes to run, spews 1409342 lines (mostly timing errors), but at least ends with tb.test_done at time 216066.7 ns: INFO: Simulation is Complete The original Micron readme.txt file covers ModelSim, NC-Verilog, and VCS. But most of my changes fix errors that would prevent correct execution on _any_ simulator. What do other Icarus users do for DDR3 simulations? - Larry |