Re: [Iverilog-devel] iverilog 10.0 compile error

[Martin W. <mai...@ma...>]

Lonnie L Gliem wrote:
> I ran into some verilog code that iverilog is failing to compile but vcs
> does.
>
The error message you are getting suggests:

1) There is a continuous assignment to rmw_busy_fifo_wen somewhere in your code.
2) You are instructing iverilog to compile SystemVerilog code.

I can reproduce your error with the attached simple test case, which results in:

   % iverilog -g2012 bug.v
   bug.v:13: error: q Unable to assign to unresolved wires.
   bug.v:15: error: q Unable to assign to unresolved wires.
   2 error(s) during elaboration.

If the continuous assignment is inside the sub module, you should also get a 
warning like:

   bug.v:18: warning: input port w is coerced to inout.

If compiled without the -g2012 option, you get a more helpful error:

   % iverilog bug.v
   bug.v:9: error: reg q; cannot be driven by primitives or continuous assignment.
   1 error(s) during elaboration.

If either of the above two conditions aren't true, it's likely a compiler bug, 
and we are going to need a failing test case to analyse.

Martin