[Iverilog-devel] File support in VHDL

[Maciej S. <mac...@ce...>]

Hi Steve,

There is a new branch [1] and associated tests [2] proposed for merging.

The patches add basic support for std.textio / ieee.std_logic_textio
libraries & while loops, and a number of minor fixes.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/86
2. https://github.com/orsonmmz/ivtest/tree/files_test