Re: [Iverilog-devel] transport delay

[Cary R. <cy...@ya...>]

I agree with Martin. I believe a non-blocking delay is the only normal RTL construct that does not filter pulses smaller than the delay. Specify blocks can also tweak this a bit using the path pulse control, but Icarus only supports full pulse filtering. The other comment is that I think the code shown is describing wire delays and Icarus does not currently support these type of delays and if I'm reading the standard correctly they should filter pulses smaller than the delay so it seems like the original assumption is incorrect.
I believe the original code shown should have generated a not supported message.

Cary 


     On Saturday, November 7, 2015 4:17 PM, Martin Whitaker <mai...@ma...> wrote:
   

 Hi Larry,

Larry Doolittle wrote:
> Friends -
>
> I want to model "transport delay" instead of "inertial delay".
> Some Verilog documents suggest that a simple
>
> reg [4:0] delay=15;
> wire #(delay * 78) dout = d;
>
> should work.  But iverilog-10 seemed to behave according to the
> inertial delay model.
>
I believe Icarus is doing the right thing. The IEEE standard doesn't use the 
terms "transport" and "inertial", but the behaviour it specifies matches the 
descriptions here:

  http://bawankule.com/verilogfaq/techqa.html

As far as I know, the only way to model a transport delay in Verilog is to use 
a non-blocking assignment.

Martin

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