Re: [Iverilog-devel] transport delay

[Martin W. <mai...@ma...>]

Hi Larry,

Larry Doolittle wrote:
> Friends -
>
> I want to model "transport delay" instead of "inertial delay".
> Some Verilog documents suggest that a simple
>
> reg [4:0] delay=15;
> wire #(delay * 78) dout = d;
>
> should work.  But iverilog-10 seemed to behave according to the
> inertial delay model.
>
I believe Icarus is doing the right thing. The IEEE standard doesn't use the 
terms "transport" and "inertial", but the behaviour it specifies matches the 
descriptions here:

   http://bawankule.com/verilogfaq/techqa.html

As far as I know, the only way to model a transport delay in Verilog is to use 
a non-blocking assignment.

Martin