[Iverilog-devel] transport delay

[Larry D. <ldo...@re...>]

Friends -

I want to model "transport delay" instead of "inertial delay".
Some Verilog documents suggest that a simple

reg [4:0] delay=15;
wire #(delay * 78) dout = d;

should work.  But iverilog-10 seemed to behave according to the
inertial delay model.

I found a workaround with a shift register,
Is there a built-in transport delay mechanism in iverilog?

In case my description here was too succinct, I posted the
code at http://recycle.lbl.gov/~ldoolitt/serdes.tar.gz

  - Larry