Re: [Iverilog-devel] Synth option and v10

[Stephen W. <st...@ic...>]

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Sure. It remains true that high-level synthesis is a low
priority so some sort of message to communicate that makes
sense, but we certainly do NOT want to be sending users to
v0.8, or even v0.9.

There are some synthesis based targets, so we do want to
support limited synthesis, we just don't want to over-promise.

On 08/20/2015 02:04 PM, Martin Whitaker wrote:
> Stephen Williams wrote:
>> Well, the synthesis is not awesome in v10, but it may actually be
>> better than v0.8, so we may want to kill that warning. We have a
>> couple of targets now that actually use synthesis. (See the blif 
>> and sizer targets.)
> 
> Also one of our users has created a target for Atmel PLDs.
> 
> There's still quite a long list of synthesis tests that no longer
> work though - see regress-v11/list - so maybe a warning that
> synthesis support is incomplete is still in order.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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