Re: [Iverilog-devel] Synth option and v10

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> Well, the synthesis is not awesome in v10, but it may actually
> be better than v0.8, so we may want to kill that warning. We have
> a couple of targets now that actually use synthesis. (See the blif
> and sizer targets.)

Also one of our users has created a target for Atmel PLDs.

There's still quite a long list of synthesis tests that no longer work though 
- see regress-v11/list - so maybe a warning that synthesis support is 
incomplete is still in order.

Martin