Re: [Iverilog-devel] Synth option and v10

[Stephen W. <st...@ic...>]

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Well, the synthesis is not awesome in v10, but it may actually
be better than v0.8, so we may want to kill that warning. We have
a couple of targets now that actually use synthesis. (See the blif
and sizer targets.)

On 08/20/2015 08:53 AM, Larry Doolittle wrote:
> Friends -
> 
> Open ended question -- what should a stable v10 say and do when 
> given the "-S" option?
> 
> Right now it starts with Warning: Synthesis is not currently being
> maintained and may not function correctly. V0.8 was the last
> release branch to have active synthesis development and support!
> 
> I venture to say that the synthesis pass in v10 is not useful for
> targeting real hardware, but the transformations can be interesting
> for understanding the abstract synthesizability of Verilog code.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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