Re: [Iverilog-devel] Synth option and v10

[Guy H. <ghu...@gm...>]

Hi Larry,

Have you looked at the sizer target?  This is something which does more
abstract analysis of the device without creating full results.

Guy

On Thursday, August 20, 2015, Larry Doolittle <ldo...@re...>
wrote:

> Friends -
>
> Open ended question -- what should a stable v10 say and do when
> given the "-S" option?
>
> Right now it starts with
> Warning: Synthesis is not currently being maintained and may not
>          function correctly. V0.8 was the last release branch to
>          have active synthesis development and support!
>
> I venture to say that the synthesis pass in v10 is not useful for targeting
> real hardware, but the transformations can be interesting for understanding
> the abstract synthesizability of Verilog code.
>
> I can trigger a handful of asserts in Icarus' synth pass by trying
> to synthesize my typical Verilog.  That doesn't seem like a show-stopper
> for v10, but it does suggest that a warning similar to what we have now
> is still called for.  Specifically:
> assert: /home/ldoolitt/git/iverilog/synth2.cc:182: failed assertion 0
> assert: /home/ldoolitt/git/iverilog/synth2.cc:232: failed assertion
> nex_out.pin_count()==1
> internal error: NetCondit::synth_async: Mux input sizes do not match. A
> size=32, B size=17
> Should I turn in bug reports?
>
> One change in the larger picture since v0.8 in 2004 is the
> emergence of yosys[1], which is open source and _can_ actually
> synthesize for real hardware.  I'd also observe that yosys
> would have a really hard time going public _without_ quality
> simulations from Icarus; it has an extensive self-test process
> based on using Icarus to compare the input Verilog with exported
> post-synthesis structural Verilog.
>
>    - Larry
>
> [1] http://www.clifford.at/yosys/
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li... <javascript:;>
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>