[Iverilog-devel] VHDL procedure calls

[Maciej S. <mac...@ce...>]

Hi Steve,

I have prepared a new branch [1] & tests [2]. New features include:

- Support for selected assignments (vhdlpp) (i.e. with x select a <= val).

- Variable initialization in the declaration line (vhdlpp).

- Procedure calls (vhdlpp), excluding support for procedures stored in
packages. Currently ivl does not handle invoking tasks using
'package_name::task_name()', though vhdlpp is able to output such code.
I do not really need it, just a side note.

- Array query functions for localparams (ivl):
$left/$high/$increment/$size/etc.


A few words of explanation for the remaining changes:
- Subprogram class is split to SubprogramHeader & SubprogramBody. My
intention was to avoid adding more system functions to
ExpFunc::elaborate() and emit(), so now they are treated in a more
generic way.

- Standard types have dedicated global objects that can be used with
SubprogramHeaders. Boolean type has been converted to a typedef to match
its definition in the VHDL standard library.

- Enumerated output ports are treated as implicit registers, if their
base type is 'logic'. As enum provides named values for a given type, it
seems valid to treat logic-based types as regs.

- Conversion of 'rising/falling_edge(sig)' to 'always begin..end
@(pos/negedge sig)' is removed, as now the same functionality is
provided with $ivlh_rising/falling_edge(). Aside from that, processes
were launched in the initalization phase, even though there were no
signal changes.

- You may also have noticed that I changed a few tests. Normally it
should not happen, but it turned out they were not entirely correct.
There are 2 extra delays (br943_944.v & vhdl_range_func.v) due to the
change described in the previous point. In vhdl_range_func.vhd
assignment type was incorrect.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/71
2. https://github.com/orsonmmz/ivtest/commits/procedure_calls_test