Re: [Iverilog-devel] error: duplicate declaration for net or variable

[Larry D. <ldo...@re...>]

Martin -

On Sun, Jun 07, 2015 at 09:17:14AM +0100, Martin Whitaker wrote:
> Larry Doolittle wrote:
> > These are simply Verilog-2005 ports that get a specification of
> > wire or reg in the module body.
> > I'm pretty sure this is supposed to be "Perfectly Legal Verilog".
> Indeed it is. I thought I'd covered all the bases when fixing the duplicate 
> name detection, but there are just too many ways of declaring ports in Verilog :-(
> Anyway, I've pushed a fix for this. Thanks for spotting it.

Thanks for fixing this so fast!
Now today's iverilog git master (commit 4068c172) and
today's yosys git master (commit de4f4dad) play nicely together.

  - Larry