Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Maciej S. <mac...@ce...>]

On 06/06/2015 06:55 AM, Larry Doolittle wrote:
> That still leaves my questions about std_ulogic and
> case-insensitivity.

As Cary suggested, I can add a patch for a configuration entry to change
letter case to either upper or lower. Preserving the original case might
be also an option, but then it can cause troubles if someone takes
advantage of VHDL's case-insensitivity.

I guess for std_ulogic the closest counterpart is "uwire logic" when it
comes to nets, but I am not sure what would be appropriate for
variables. If someone has an idea, I can also add it, this should not be
a very complex change.

Regards,
Orson