Re: [Iverilog-devel] error: duplicate declaration for net or variable

[Martin W. <mai...@ma...>]

Larry Doolittle wrote:
> These are simply Verilog-2005 ports that get a specification of
> wire or reg in the module body.  Abridged version of the first example,
> that's enough to trigger the error:
>
> module MyMem #(parameter DataWidth = 4) (
>    output [DataWidth-1:0] Data_o);
>    reg [DataWidth-1:0] Data_o;
> endmodule
>
> I'm pretty sure this is supposed to be "Perfectly Legal Verilog".
>
Indeed it is. I thought I'd covered all the bases when fixing the duplicate 
name detection, but there are just too many ways of declaring ports in Verilog :-(

I am surprised that there wasn't a single example like this in the test suite.

Anyway, I've pushed a fix for this. Thanks for spotting it.

Martin