Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Cary -

On Sat, Jun 06, 2015 at 04:08:22PM -0700, Larry Doolittle wrote:
> On Sat, Jun 06, 2015 at 08:47:56PM +0000, Cary R. wrote:
> > I suppose you could argue all items in the module since most things can be accessed using various scoping rules. Though only the interface should be enough for most real examples.

Xilinx and its customers consider the module name, generics,
and ports to be an API.  I've _never_ heard about anyone reaching 
into their simulations, or even talk about it.  That is not even
possible for synthesizable code, which is the focus of this VHDL work.

Just trying to agree as strongly as possible.

  - Larry