Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Cary -

On Sat, Jun 06, 2015 at 08:47:56PM +0000, Cary R. wrote:
> Would adding an option to the VHDL config file for a given module to emit it/just the interface as upper or lower case solve your problem. I would assume the default would be lower case like we currently do. By interface I am assuming parameters, ports and the actual module name. I suppose you could argue all items in the module since most things can be accessed using various scoping rules. Though only the interface should be enough for most real examples.

Of 10766 parameter names in Xilinx XST 12.1 Verilog unisims, only
26 are not all-caps, and a spot check of those show they are
not part of the API.

Out of ~17117 generics and ports in unisim_VCOMP.vhd, 11 are not all-caps.
Eight of those are in one pathological component (selfheal_oserdese1_vhd).

Out of 1118 components listed in unisim_VCOMP.vhd, only four names are not
all-caps (bscntrl_iserdese1_vhd, ice_iserdese1_vhd, plg_oserdese1_vhd,
selfheal_oserdese1_vhd).

So, yes.

Maybe more work, but arguably better, would be to be case-retentive
based on the component declaration.  No need for configuration.

  - Larry