Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

Just talking to myself on a Friday night, I guess.

On Fri, Jun 05, 2015 at 09:55:41PM -0700, Larry Doolittle wrote:
> On Fri, Jun 05, 2015 at 08:51:18PM -0700, Larry Doolittle wrote:
> > I'm still struggling to understand how to connect a .vhd file
> > that says
> > library unisim;
> >   use unisim.vcomponents.all;
> > with all the component declarations in
> > $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
> If I can figure out how to pass "-L foo" to vhdlpp,
> I think I can get through this step.

Create a what.cfg file containing
+vhdl-libdir+foo
and then a normal iverilog invocation (with the -cwhat.cfg option)
processes the file
>   foo/unisim/vcomponents.pkg

> And if that file is a (trimmed down and hacked) copy
> of $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd, it seems
> to emit the Verilog I'm looking for.
> That still leaves my questions about std_ulogic and
> case-insensitivity.

The VHDL preprocessor correctly handles case-insensitive
matches between the component declaration and the instantiation.
But the Verilog it emits has the instantiation's name, ports, and
parameters/generics all converted to lower case.  This does
not match the implementation in $XILINX/verilog/src/unisims/*.v.
In fact Xilinx seems to have "standardized" on upper case for
all those names.  So the compilation as a whole fails.

I guess this is an artifact of trying to use the Verilog unisims;
if there were a chance that all the test-bench-like constructs
in their VHDL unisims would be accepted by iverilog/vhdlpp,
the case-insensitive match (as implemented by converting all VHDL
identifiers to lower case in the emitted Verilog) would work fine.

   - Larry