Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

On Fri, Jun 05, 2015 at 08:51:18PM -0700, Larry Doolittle wrote:
> I'm still struggling to understand how to connect a .vhd file
> that says
> library unisim;
>   use unisim.vcomponents.all;
> with all the component declarations in
> $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

If I can figure out how to pass "-L foo" to vhdlpp,
I think I can get through this step.  When I add that
to a by-hand invocation of vhdlpp, I can follow along
and get it to process the file
  foo/unisim/vcomponents.pkg
And if that file is a (trimmed down and hacked) copy
of $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd, it seems
to emit the Verilog I'm looking for.

That still leaves my questions about std_ulogic and
case-insensitivity.

   - Larry