[Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

I'm still struggling to understand how to connect a .vhd file
that says

library unisim;
  use unisim.vcomponents.all;

with all the component declarations in

$XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

and from there to the Verilog unisim implementations in
$XILINX/verilog/src/unisims/*.v.

We talked before, and I'm pretty sure that last step is
a better option than the VHDL unisim implementations in
$XILINX/vhdl/src/unisims/primitive/*.vhd.

Do you have this working?  Can you give me a recipe, or
hint, or anything?

BTW,
iverilog -g2005-sv $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
crashes and burns badly.  Hundreds of
Can't find type name `std_ulogic'
among other things.

I'm still fumbling around, maybe making a little progress.
Isn't VHDL supposed to be case-insensitive?  I can't get
an instantiation of ibufds to match a component IBUFDS.

   - Larry