Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> That shares the literal bits that are the time value, but it
> does not account for the semantics of time. If it did, it would
> scale time values to local units as they cross module boundaries.
> That is the crux of the problem that Orson is facing.
>
As I wrote before, the 'time' data type has no special semantics in Verilog - 
it's just a 64-bit vector.

We have already identified a solution to the scaling problem - just make sure 
that all translated VHDL code has the same time units. Then you can safely 
pass time values between modules using the 'time' data type.

Of course you will run into problems if you pass time values to native Verilog 
modules which have their own (different) timescale - but that's a problem 
inherent in Verilog, and not one I think we should be trying to fix.

Martin